Each CPU has access to 512 32-bit long words (2 KB) of instructions and data. / Access to shared memory (32 KB RAM; 32 KB ROM) is round-robin / Each cog also has two dedicated hardware counters and two special "video registers" for use in generating PAL, NTSC, VGA, servo-control, or other timing signals.
at 80 MHz, the interpreted Spin language executes approximately 80,000 instruction-tokens per second on each core / machine-language instructions take 4 clock-cycles to execute, resulting in 20 MIPS per cog
Ouch, 4 cycles per instruction. Slow... 20MIPS can be achieved on AVR with only a 20mhz crystal.
But i guess the advantage is the multiple cores.
For something in a similar vein, but with more grunt:
an interesting device / less than $5 in quantity / 96-pin dual-row BGA package about the size of a nickel.
a microprocessor with a lot of I/O. It fulfills the role of PLD or FPGA on your printed-circuit board, but you talk to it in C
an internal multithreaded microprocessor to “fake” the functions of programmable logic. / And you define those functions entirely with C code. / It’s just straight C programming—for hardware.
about 700 MHz / toggle the state of any I/O pin on any clock edge. That’s plenty fast enough for Ethernet, USB, audio input/output, PWM / you get to define what those interfaces are and what pins they’re attached to. / redefining peripherals as easily as updating a boot ROM. / XMOS provides code libraries for all the usual interfaces.
In a sense, each and every I/O interface is backed up by its own dedicated I/O processor that can massage data, filter inputs, encrypt or decrypt packets, and more. The processor is just as happy to do processing as it is handling I/O tasks, so the XS1-S is both a processor chip and a logic chip in one.
About the only special-purpose logic on the chip is the 480 Mbit/sec USB PHY and a four-channel ADC (12 bits, 1M samples/sec).
eight threads, so you’ve got eight virtual processors / think of it as eight independent CPUs, each running at one-eighth of the chip’s overall clock frequency. There is no elaborate time slicing or preemptive multitasking; the XS1-S chip simply shifts to the next thread on each clock cycle. / It’s extremely simple, very predictable, and totally deterministic.
$15, ARM Cortex-M4F core, 1 MB Flash, 192 KB RAM, lots of GPIO, USB OTG for both initial programming/debug, and mounting devices.
I maintain the Mac drivers for MESS. We strictly emulate the actual chips in the actual machines
we emulate the actual 5380 and 5394/96 SCSI chips and simulate a generic SCSI HDD at the other end of the SCSI bus
Which could be useful for simulating these ICs on an FPGA/CLPD
Course, another approach would be to build a pair of AVRs on an FPGA as softcores (which are available at OpenCores IIRC), and use the existing code. Then rebuilding the device for other purposes is just a reconfig and recode, not a physical rebuild.
The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit address space
Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR FLASH, NAND FLASH and SRAM. Some Blackfin also include mass-storage interfaces such as ATAPI, and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.
a DMA engine that can operate between any of its peripherals and main (or external) memory. typically have a dedicated DMA channel for each peripheral, which enables very high throughput
Development boards etc
$25 FPGA board. Very minimalist, pretty much just power regulation and pinout adaption. Altera Cyclone II EP2C5T144. Requires $9 programming cable from same seller. http://cgi.ebay.com/itm/271021067627