Here is something that just dawned on me today. I had noticed that the Mac 512K, and especially 128K DRAM is failing or has failed at an alarming rate. There are replacements so thats fine. But, isnt DRAM not made anymore technically? What happens when 30 pin SIMMs start dropping like flies, I dont think they are made anymore.
I know we have awhile before we start thinking about that and taking it into consideration, but we may start rolling around thoughts in our head to see if its possible to convert the old school DRAM timings with a CPLD to a more modern, DDR3 SODIMM timing. Not to mention just 1 stick would fill the entire addressing capacity, if not more.
I worry about all the silicon in general... Ultimately I'd be great to have FPGA based hardware that could drop into most systems with the main ports needed without being able to tell it's an entirely new logic board. Maybe one day...
If I'm understanding the problem correctly, the obvious entry point for moisture would be the pins. Might flooding the chink in the armor with the likes of clear nail polish after a thorough baking be a reasonable stopgap measure
Do you think 72pin SIMMs will be suffering a similar fate? I'm currently on hiatus at the prototyping point for my 72pin->30pin SIMM & Discrete DRAM MoBo component level converter for the IIsi's memory banks. Such may someday come in handy?
I have often thought that it should be possible to create SRAM based SIMMs with a CPLD and maybe a buffer chip to demux the multiplexed addresses (computer send address in row part and column part, using the same pins, SRAM expects address all at once).
That's be a pain, but at least there's a relatively simple way forward with modernish parts if the old DRAM all starts to die at once.
I've had thoughts about this as well. Regular old SDRAM could probably be made to work with a CPLD and some external latch/buffer ICs (it's all 3.3v, but it's at least pretty tame compared to DDR). I haven't worked out all the details mentally, but SDRAM's control signals are intentionally pretty close to old async DRAM. Loading the mode register initially could be a bit of a pain in a CPLD, but probably not the end of the world.
That said, some of the timings are pretty close. For example, Tcac on a 60 ns DRAM is 20 ns; that's the same as a CL=2 on 100 MHz SDRAM, and that assumes you catch the signal right on the edge (remember, SDRAM runs off a clock, while the DRAM timing generator in the host computer will be running off an entirely different clock). Timing could be pretty marginal. Still, not a bad thought, especially for larger capacity SIMMs.