"Our attempts to clone DayStar PDS adapters have been abandoned." gamba2
I think it's well past time to revisit that project. ISTR techknight telling me that the adaptation moves the memory addressing of the SE/30 PDS to another part of the memory map where the IIci Cache Card resides. I don't know how that works, but it's been done before.
I'm taking my usual fumble-fingered stab at developing a ridiculous multifunction card for the SE/30. So of course, I'm looking to make provisions for hanging as much crap off the thing as is humanly/technically possible, interrupt permitting.*** Rearranging the PDS signals to match the IIci Cache card I can crib from DCaDftMF. If the lines for the memory displacement PAL are identified by someone who has an adapter card, I can easily add pads/thru-holes for it to hold in reserve along with the remapped, but unpopulated EuroDin120 connection for such a time as the PAL programming project might be accomplished. Obviously that would need to be done by others. :rolleyes:
Thanks to mcdermd, I've got a 16MHz PowerCache "accelerator" that I'd dearly love to stick on top of that sucker. There may be no clock rate enhancement, but I figure Daystar wouldn't have marketed this card if "merely" adding cache didn't give give the 16MHz Mac II series a serious kick in the pants, just as the Cache Card does for the IIci at its native 25MHz clock rate.
Is it possible to jumper additional interrupt lines from wherever appropriate in the GLUE/NuChip architecture of the SE/30 and its IIcx sire which might then be addressable by an SE/30 with the IIfx ROM SIMM or a hacked variant thereof on board? I've already got plans for jumpering at least 10 lines to the RidiculousCard from the SE/30 MoBo, so WTH? ;-D
I'm not familiar with the more advanced bus arbitration signals of the 030, but the PDS and the cache card don't have a dedicated address space. They're on the processor bus. They're whatever addresses they choose to respond to.
Hrmmm? Thanks for that bit of info. All the adaptations for the SE/30 on gamba show only two cards with the adapter. I wonder which interrupt the Cache slot uses, could that be the hitch? ***
I mentioned this to trag and he said that someone will have to do this eventually. Things IRL have do a way of soaking up development time. Especially the joyous lavishing of time and attention on the kiddos. Ain't nothin' in this life more important than that!
"If you are determined to design an expansion card other than a cache memory card, you should be aware of the following limitations.
The absence of some machine specific signals imposes severe restrictions restrictions on your design.
I'm guessing that the . . .
LCIII PDS has no PLD on board and three interrupt lines available . . .
LCIII DevNote quoted:
/SLOTIRQ.C Slot $C interrupt request. Not supported by the Macintosh LC III.
/SLOTIRQ.D Slot $D interrupt request. Not supported by the Macintosh LC III.
/SLOTIRQ.E Slot $E interrupt request. Generates an interrupt corresponding to a device in NuBus slot $E.
SLOT $E = SE/30 Video
IRQ 4/SLOT $C = unused in SE/30 (as opposed to +not supported+)
IRQ 4/SLOT $C = unused in SE/30 (as opposed to +not supported+)
WAG = PowerCache requires an IRQ line
No IRQ line available on IIci Cache Slot
(maybe?) PLD Adapts IRQ generated on the PowerCache
WAG: IIci = No gots Slot $E but the LCIII does, the SE/30 uses Slot $E for Video.
PLD remaps Slot $E to the unused IRQ in the gamba diagrams?
dunno . . . off to work, hope this makes a little bit of sense to someone with a clue. :/
Boo-Boo fixup: Had IRQ4/Slot $C twice, meant 4/5 and C/D.
IRQ 1/SLOT $9 = available on SE/30 PDS & NuBus Slot in IIcx
IRQ 2/SLOT $A = available on SE/30 PDS & NuBus Slot in IIcx
IRQ 3/SLOT $B = available on SE/30 PDS & NuBus Slot in IIcx
IRQ 4/SLOT $C = unused in SE/30 (as opposed to not supported )
IRQ 5/SLOT $D = unused in SE/30 (as opposed to not supported )
SLOT $E = SE/30 Video
IIci Video addresses in Slot $0, but "memory addresses in $B of NuBus address space?"
IIci Devnote shows no interrupts available in Cache Slot, which differs from DCaDftMF
Pin C26 = n.c. in DevNote = IPL0 in DCaDftMF
Pin C25 = n.c. in DevNote = IPL1 in DCaDftMF
Pin C12 = n.c. in DevNote = IPL2 in DCaDftMF
IPL0-2 would be the only interrupts common to all three: SE/30 PDS, LCIII PDS and the IIci Cache Slot, which has no IRQ lines available . . .
The Mac II adapter has no adaptation on it, plugging directly into CPU and PMMU IIRC. I'll assume that the socketed PowerCache accelerators needed no adaptation either, having access to every CPU signal in the same manner.
I'm tired and confused again, I've probably mangled numbers and letters, but my gut tells me there has to be something in there somewhere that sheds at least the tiniest bit of light on the function of the CPLD adaptation . . .
So, I'm confused on what slots or interrupts have to do with a cache card.
The whole point of a cache card, I thought, is when the CPU does a read operation (from a cacheable address), the cache can return it to the CPU faster, and hopefully burst transfer the entire cache line, than RAM ordinarily would. That's it. There's no driver that talks to a NuBus Slot, the cache card doesn't do anything to trigger a host processor interrupt (and corresponding OS software handling).
I don't know what it has to do with a cache card, but an accelerator in the IIci cache slot is probably a whole different kettle of worms. The PowerCache works in the IIci cache slot and in the LCIII PDS @ $E without a hitch. Only the lines have been changed to protect signal integrity and a few SMT doo-dads stuck on here or there for good measure on the LCIII adapters.
But in the SE/30 you need the CPLD (i think that's what trag called it) on the adapter, the line conditioning doo-dads as well as the signal switcharoo and $E just happens to be the slot address of the SE/30's video subsystem.
My hunch is that this is more than coincidental. Maybe yes, maybe no, but that's the one clue I've got so far and I'm stickin' with it!
I tried to find the roadmap pic of PowerCache adaptation for the various Macintosh models and it didn't turn up.
I think I may have figured out the source of confusion. In DCaDftMF pp.389-392 list the signals available on the IIci cache slot. The bolded entries are signals Apple placed on the connector for diagnostics purposes only and would be the jumping off point for those "determined to design an expansion card other than a cache memory card," such as the PowerCache accelerators.
My theory is that something about Daystar's implementation using machine level interrupts /IPL0-IPL2 or some other "extraneous" signals available for operations "other than cache" puts a hurt on the function of cards at location $E that are not designed to operate within the framework of the Slot Manager operations. The video subsystem of the SE/30 may appear to occupy $E to Sot Manager, but there was no reason for Apple to operate within its own Slot Manager design guidelines for a "card" in a slot location in the SE/30 that's unimplemented in hardware.
My theory is that operations of the PowerCache accelerator interfere only with those operations of slot $E that fall outside standard Slot Manager Design guidelines. Slot $E would therefore be fully functional in six slot Macs and the LCIII PDS that fall within those standard Slot Manager operations . . .
...but well and truly bork the SE/30's video subsystem, hence, the CPLD adaptation?
Message was edited by: Trash80toHP_Mini - the line appears twice in the edit window, but shows up in the edited message only once . . .
Message was edited by: Trash80toHP_Mini - AGAIN - dunno, but post editing game is over.
there appears to be a bug in the "edit" process that drops the above sentence out of the edited post.
got it! a line beginning with my habitual double space barred ellipse location comments out the line, but if the last period of the ellipse abuts the next letter in the line, it appears inset as above.
DCaDftMFH p.460 has additional information about memory addressing of the NuBus signal in the SE/30 that would seem to support my Slot E borkage theory.
Quick snooze: still tired, but realized that's p.460 in GttMFH2e, DCaDftMFH doesn't even go that high. :/
/NUBUS - In the Macintosh SE/30, indicates address in the memory range $6000 0000 to $FFFF FFFF. This signal is active when the CPU addresses the built-in video display. (Expansion cards can use this signal and further decode the slot address ranges to avoid conflict with the video logic.
Sounds like a right fine application for a CPLD to me. Dunno, whatchathink?
Pseudo-slot video in the Macintosh IIci
Like the built-in video in the Macintosh SE/30, the video interface in the Macintosh IIci simulates some features of a Macintosh II Video Card in a NuBus expansion slot. By simulating the features of an expansion card in a slot, the Macintosh IIci can share common System ROM with the other Macintosh models that use the MC68030 processor. This simulation of a video card in a NuBus slot is called pseudo-slot video.
The video screen buffer in the Macintosh IIci occupies memory starting at $0000_0000 in physical address space. Using the memory management unit in the MC68030, the Macintosh IIci maps the screen buffer to logical address space starting at $FB000_0000. That address space was chosen because it is the same as the address space used by expansion slot $B in the six-slot in the six-slot models of the Macintosh II family.
That $B was an intentional choice in the IIci design jibes with the above tidbit about operations of the PowerCache Accelerators and my guess that they step all over Interrupt/Slot/Pseudo-Slot assignments of the IIsi and SE/30.
Driving the video subsystems of either appears to me to require some kind of logical intervention to sidestep Slot Manager operations as well as the memory mapping issue techknight had previously noted.
The second discovery would be the existence of two versions of the Twin-Slot Adapter for the IIsi.
Hopefully the differences between the two versions will shed some light on the Cloning Project requirements for someone competent. My guess is that later (read faster better, more likely to wind up in an SE/30) PowerCache Cards had on-board ROM and circuitry mods circumventing the need for the drastic interventions necessary for compatibility with previous models.
I'll also guess that the location of the last remaining IC and pin assignments of U1 on the simplified Rev.2 adapter will be crucial in reverse engineering.
WAG: the unimplemented pads at U3 on the Rev.2 adapter suggest to me the possibility that a Rev.1.5 version was produced with backward compatibility with earlier PowerCache models, possibly another crucial tidbit?
Dunno, I think I've done about all that I can at this point. I don't have any of the adapters linked here and I've never even seen the SE/30 adapter which puts me at a severe disadvantage. Pics would be greatly appreciated, posting them in the NuBus Mafia project on 'fritter would seem to be the most useful for later iterations of the cloning project.
I'll get the lead out and post pics there of the LCIII adapter myself, or have someone competent post them for me!